/***************************************************************************//**
* \file cyreg_peri.h
*
* \brief
* PERI register definition header
*
* \note
* Generator version: 1.6.0.481
* Database revision: TVIIBH4M_PR3_0
*
********************************************************************************
* \copyright
* Copyright 2016-2021, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/

#ifndef _CYREG_PERI_H_
#define _CYREG_PERI_H_

#include "cyip_peri_v3.h"

/**
  * \brief Peripheral group structure (PERI_GR0)
  */
#define CYREG_PERI_GR0_SL_CTL           ((volatile un_PERI_GR_SL_CTL_t*) 0x40004010UL)

/**
  * \brief Peripheral group structure (PERI_GR1)
  */
#define CYREG_PERI_GR1_SL_CTL           ((volatile un_PERI_GR_SL_CTL_t*) 0x40004050UL)

/**
  * \brief Peripheral group structure (PERI_GR2)
  */
#define CYREG_PERI_GR2_SL_CTL           ((volatile un_PERI_GR_SL_CTL_t*) 0x40004090UL)

/**
  * \brief Peripheral group structure (PERI_GR3)
  */
#define CYREG_PERI_GR3_CLOCK_CTL        ((volatile un_PERI_GR_CLOCK_CTL_t*) 0x400040C0UL)
#define CYREG_PERI_GR3_SL_CTL           ((volatile un_PERI_GR_SL_CTL_t*) 0x400040D0UL)

/**
  * \brief Peripheral group structure (PERI_GR4)
  */
#define CYREG_PERI_GR4_CLOCK_CTL        ((volatile un_PERI_GR_CLOCK_CTL_t*) 0x40004100UL)
#define CYREG_PERI_GR4_SL_CTL           ((volatile un_PERI_GR_SL_CTL_t*) 0x40004110UL)

/**
  * \brief Peripheral group structure (PERI_GR5)
  */
#define CYREG_PERI_GR5_CLOCK_CTL        ((volatile un_PERI_GR_CLOCK_CTL_t*) 0x40004140UL)
#define CYREG_PERI_GR5_SL_CTL           ((volatile un_PERI_GR_SL_CTL_t*) 0x40004150UL)

/**
  * \brief Peripheral group structure (PERI_GR6)
  */
#define CYREG_PERI_GR6_CLOCK_CTL        ((volatile un_PERI_GR_CLOCK_CTL_t*) 0x40004180UL)
#define CYREG_PERI_GR6_SL_CTL           ((volatile un_PERI_GR_SL_CTL_t*) 0x40004190UL)

/**
  * \brief Peripheral group structure (PERI_GR8)
  */
#define CYREG_PERI_GR8_CLOCK_CTL        ((volatile un_PERI_GR_CLOCK_CTL_t*) 0x40004200UL)
#define CYREG_PERI_GR8_SL_CTL           ((volatile un_PERI_GR_SL_CTL_t*) 0x40004210UL)

/**
  * \brief Peripheral group structure (PERI_GR9)
  */
#define CYREG_PERI_GR9_CLOCK_CTL        ((volatile un_PERI_GR_CLOCK_CTL_t*) 0x40004240UL)
#define CYREG_PERI_GR9_SL_CTL           ((volatile un_PERI_GR_SL_CTL_t*) 0x40004250UL)

/**
  * \brief Trigger group (PERI_TR_GR0)
  */
#define CYREG_PERI_TR_GR0_TR_CTL0       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40008000UL)
#define CYREG_PERI_TR_GR0_TR_CTL1       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40008004UL)
#define CYREG_PERI_TR_GR0_TR_CTL2       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40008008UL)
#define CYREG_PERI_TR_GR0_TR_CTL3       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000800CUL)
#define CYREG_PERI_TR_GR0_TR_CTL4       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40008010UL)
#define CYREG_PERI_TR_GR0_TR_CTL5       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40008014UL)
#define CYREG_PERI_TR_GR0_TR_CTL6       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40008018UL)
#define CYREG_PERI_TR_GR0_TR_CTL7       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000801CUL)

/**
  * \brief Trigger group (PERI_TR_GR1)
  */
#define CYREG_PERI_TR_GR1_TR_CTL0       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40008400UL)
#define CYREG_PERI_TR_GR1_TR_CTL1       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40008404UL)
#define CYREG_PERI_TR_GR1_TR_CTL2       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40008408UL)
#define CYREG_PERI_TR_GR1_TR_CTL3       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000840CUL)
#define CYREG_PERI_TR_GR1_TR_CTL4       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40008410UL)
#define CYREG_PERI_TR_GR1_TR_CTL5       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40008414UL)
#define CYREG_PERI_TR_GR1_TR_CTL6       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40008418UL)
#define CYREG_PERI_TR_GR1_TR_CTL7       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000841CUL)

/**
  * \brief Trigger group (PERI_TR_GR2)
  */
#define CYREG_PERI_TR_GR2_TR_CTL0       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40008800UL)
#define CYREG_PERI_TR_GR2_TR_CTL1       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40008804UL)
#define CYREG_PERI_TR_GR2_TR_CTL2       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40008808UL)
#define CYREG_PERI_TR_GR2_TR_CTL3       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000880CUL)
#define CYREG_PERI_TR_GR2_TR_CTL4       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40008810UL)
#define CYREG_PERI_TR_GR2_TR_CTL5       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40008814UL)
#define CYREG_PERI_TR_GR2_TR_CTL6       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40008818UL)
#define CYREG_PERI_TR_GR2_TR_CTL7       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000881CUL)
#define CYREG_PERI_TR_GR2_TR_CTL8       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40008820UL)
#define CYREG_PERI_TR_GR2_TR_CTL9       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40008824UL)
#define CYREG_PERI_TR_GR2_TR_CTL10      ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40008828UL)
#define CYREG_PERI_TR_GR2_TR_CTL11      ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000882CUL)
#define CYREG_PERI_TR_GR2_TR_CTL12      ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40008830UL)
#define CYREG_PERI_TR_GR2_TR_CTL13      ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40008834UL)
#define CYREG_PERI_TR_GR2_TR_CTL14      ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40008838UL)
#define CYREG_PERI_TR_GR2_TR_CTL15      ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000883CUL)

/**
  * \brief Trigger group (PERI_TR_GR3)
  */
#define CYREG_PERI_TR_GR3_TR_CTL0       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40008C00UL)
#define CYREG_PERI_TR_GR3_TR_CTL1       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40008C04UL)
#define CYREG_PERI_TR_GR3_TR_CTL2       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40008C08UL)
#define CYREG_PERI_TR_GR3_TR_CTL3       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40008C0CUL)
#define CYREG_PERI_TR_GR3_TR_CTL4       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40008C10UL)
#define CYREG_PERI_TR_GR3_TR_CTL5       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40008C14UL)
#define CYREG_PERI_TR_GR3_TR_CTL6       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40008C18UL)
#define CYREG_PERI_TR_GR3_TR_CTL7       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40008C1CUL)

/**
  * \brief Trigger group (PERI_TR_GR4)
  */
#define CYREG_PERI_TR_GR4_TR_CTL0       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009000UL)

/**
  * \brief Trigger group (PERI_TR_GR5)
  */
#define CYREG_PERI_TR_GR5_TR_CTL0       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009400UL)
#define CYREG_PERI_TR_GR5_TR_CTL1       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009404UL)
#define CYREG_PERI_TR_GR5_TR_CTL2       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009408UL)
#define CYREG_PERI_TR_GR5_TR_CTL3       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000940CUL)
#define CYREG_PERI_TR_GR5_TR_CTL4       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009410UL)
#define CYREG_PERI_TR_GR5_TR_CTL5       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009414UL)
#define CYREG_PERI_TR_GR5_TR_CTL6       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009418UL)
#define CYREG_PERI_TR_GR5_TR_CTL7       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000941CUL)
#define CYREG_PERI_TR_GR5_TR_CTL8       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009420UL)
#define CYREG_PERI_TR_GR5_TR_CTL9       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009424UL)
#define CYREG_PERI_TR_GR5_TR_CTL10      ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009428UL)
#define CYREG_PERI_TR_GR5_TR_CTL11      ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000942CUL)

/**
  * \brief Trigger group (PERI_TR_GR6)
  */
#define CYREG_PERI_TR_GR6_TR_CTL0       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009800UL)
#define CYREG_PERI_TR_GR6_TR_CTL1       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009804UL)
#define CYREG_PERI_TR_GR6_TR_CTL2       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009808UL)
#define CYREG_PERI_TR_GR6_TR_CTL3       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000980CUL)
#define CYREG_PERI_TR_GR6_TR_CTL4       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009810UL)
#define CYREG_PERI_TR_GR6_TR_CTL5       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009814UL)
#define CYREG_PERI_TR_GR6_TR_CTL6       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009818UL)
#define CYREG_PERI_TR_GR6_TR_CTL7       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000981CUL)
#define CYREG_PERI_TR_GR6_TR_CTL8       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009820UL)
#define CYREG_PERI_TR_GR6_TR_CTL9       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009824UL)
#define CYREG_PERI_TR_GR6_TR_CTL10      ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009828UL)
#define CYREG_PERI_TR_GR6_TR_CTL11      ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000982CUL)
#define CYREG_PERI_TR_GR6_TR_CTL12      ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009830UL)
#define CYREG_PERI_TR_GR6_TR_CTL13      ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009834UL)
#define CYREG_PERI_TR_GR6_TR_CTL14      ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009838UL)

/**
  * \brief Trigger group (PERI_TR_GR7)
  */
#define CYREG_PERI_TR_GR7_TR_CTL0       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009C00UL)
#define CYREG_PERI_TR_GR7_TR_CTL1       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009C04UL)
#define CYREG_PERI_TR_GR7_TR_CTL2       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009C08UL)
#define CYREG_PERI_TR_GR7_TR_CTL3       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009C0CUL)
#define CYREG_PERI_TR_GR7_TR_CTL4       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009C10UL)
#define CYREG_PERI_TR_GR7_TR_CTL5       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009C14UL)
#define CYREG_PERI_TR_GR7_TR_CTL6       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009C18UL)
#define CYREG_PERI_TR_GR7_TR_CTL7       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009C1CUL)
#define CYREG_PERI_TR_GR7_TR_CTL8       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009C20UL)
#define CYREG_PERI_TR_GR7_TR_CTL9       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009C24UL)
#define CYREG_PERI_TR_GR7_TR_CTL10      ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009C28UL)
#define CYREG_PERI_TR_GR7_TR_CTL11      ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009C2CUL)

/**
  * \brief Trigger group (PERI_TR_GR8)
  */
#define CYREG_PERI_TR_GR8_TR_CTL0       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000A000UL)
#define CYREG_PERI_TR_GR8_TR_CTL1       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000A004UL)
#define CYREG_PERI_TR_GR8_TR_CTL2       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000A008UL)
#define CYREG_PERI_TR_GR8_TR_CTL3       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000A00CUL)
#define CYREG_PERI_TR_GR8_TR_CTL4       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000A010UL)
#define CYREG_PERI_TR_GR8_TR_CTL5       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000A014UL)
#define CYREG_PERI_TR_GR8_TR_CTL6       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000A018UL)
#define CYREG_PERI_TR_GR8_TR_CTL7       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000A01CUL)

/**
  * \brief Trigger group (PERI_TR_GR9)
  */
#define CYREG_PERI_TR_GR9_TR_CTL0       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000A400UL)
#define CYREG_PERI_TR_GR9_TR_CTL1       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000A404UL)
#define CYREG_PERI_TR_GR9_TR_CTL2       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000A408UL)
#define CYREG_PERI_TR_GR9_TR_CTL3       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000A40CUL)
#define CYREG_PERI_TR_GR9_TR_CTL4       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000A410UL)
#define CYREG_PERI_TR_GR9_TR_CTL5       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000A414UL)
#define CYREG_PERI_TR_GR9_TR_CTL6       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000A418UL)
#define CYREG_PERI_TR_GR9_TR_CTL7       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000A41CUL)
#define CYREG_PERI_TR_GR9_TR_CTL8       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000A420UL)
#define CYREG_PERI_TR_GR9_TR_CTL9       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000A424UL)
#define CYREG_PERI_TR_GR9_TR_CTL10      ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000A428UL)

/**
  * \brief Trigger group (PERI_TR_GR10)
  */
#define CYREG_PERI_TR_GR10_TR_CTL0      ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000A800UL)
#define CYREG_PERI_TR_GR10_TR_CTL1      ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000A804UL)
#define CYREG_PERI_TR_GR10_TR_CTL2      ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000A808UL)
#define CYREG_PERI_TR_GR10_TR_CTL3      ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000A80CUL)
#define CYREG_PERI_TR_GR10_TR_CTL4      ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000A810UL)

/**
  * \brief Trigger group (PERI_TR_GR11)
  */
#define CYREG_PERI_TR_GR11_TR_CTL0      ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000AC00UL)
#define CYREG_PERI_TR_GR11_TR_CTL1      ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000AC04UL)
#define CYREG_PERI_TR_GR11_TR_CTL2      ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000AC08UL)
#define CYREG_PERI_TR_GR11_TR_CTL3      ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000AC0CUL)
#define CYREG_PERI_TR_GR11_TR_CTL4      ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000AC10UL)

/**
  * \brief Trigger group (PERI_TR_GR12)
  */
#define CYREG_PERI_TR_GR12_TR_CTL0      ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000B000UL)
#define CYREG_PERI_TR_GR12_TR_CTL1      ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000B004UL)
#define CYREG_PERI_TR_GR12_TR_CTL2      ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000B008UL)
#define CYREG_PERI_TR_GR12_TR_CTL3      ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000B00CUL)
#define CYREG_PERI_TR_GR12_TR_CTL4      ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000B010UL)

/**
  * \brief Trigger 1-to-1 group (PERI_TR_1TO1_GR0)
  */
#define CYREG_PERI_TR_1TO1_GR0_TR_CTL0  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C000UL)
#define CYREG_PERI_TR_1TO1_GR0_TR_CTL1  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C004UL)
#define CYREG_PERI_TR_1TO1_GR0_TR_CTL2  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C008UL)
#define CYREG_PERI_TR_1TO1_GR0_TR_CTL3  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C00CUL)
#define CYREG_PERI_TR_1TO1_GR0_TR_CTL4  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C010UL)
#define CYREG_PERI_TR_1TO1_GR0_TR_CTL5  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C014UL)
#define CYREG_PERI_TR_1TO1_GR0_TR_CTL6  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C018UL)
#define CYREG_PERI_TR_1TO1_GR0_TR_CTL7  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C01CUL)
#define CYREG_PERI_TR_1TO1_GR0_TR_CTL8  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C020UL)
#define CYREG_PERI_TR_1TO1_GR0_TR_CTL9  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C024UL)
#define CYREG_PERI_TR_1TO1_GR0_TR_CTL10 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C028UL)
#define CYREG_PERI_TR_1TO1_GR0_TR_CTL11 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C02CUL)

/**
  * \brief Trigger 1-to-1 group (PERI_TR_1TO1_GR1)
  */
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL0  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C400UL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL1  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C404UL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL2  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C408UL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL3  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C40CUL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL4  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C410UL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL5  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C414UL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL6  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C418UL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL7  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C41CUL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL8  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C420UL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL9  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C424UL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL10 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C428UL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL11 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C42CUL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL12 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C430UL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL13 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C434UL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL14 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C438UL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL15 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C43CUL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL16 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C440UL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL17 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C444UL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL18 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C448UL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL19 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C44CUL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL20 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C450UL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL21 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C454UL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL22 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C458UL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL23 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C45CUL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL24 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C460UL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL25 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C464UL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL26 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C468UL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL27 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C46CUL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL28 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C470UL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL29 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C474UL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL30 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C478UL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL31 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C47CUL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL32 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C480UL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL33 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C484UL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL34 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C488UL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL35 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C48CUL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL36 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C490UL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL37 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C494UL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL38 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C498UL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL39 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C49CUL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL40 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C4A0UL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL41 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C4A4UL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL42 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C4A8UL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL43 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C4ACUL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL44 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C4B0UL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL45 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C4B4UL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL46 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C4B8UL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL47 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C4BCUL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL48 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C4C0UL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL49 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C4C4UL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL50 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C4C8UL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL51 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C4CCUL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL52 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C4D0UL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL53 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C4D4UL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL54 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C4D8UL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL55 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C4DCUL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL56 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C4E0UL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL57 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C4E4UL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL58 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C4E8UL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL59 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C4ECUL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL60 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C4F0UL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL61 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C4F4UL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL62 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C4F8UL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL63 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C4FCUL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL64 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C500UL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL65 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C504UL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL66 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C508UL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL67 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C50CUL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL68 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C510UL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL69 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C514UL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL70 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C518UL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL71 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C51CUL)

/**
  * \brief Trigger 1-to-1 group (PERI_TR_1TO1_GR2)
  */
#define CYREG_PERI_TR_1TO1_GR2_TR_CTL0  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C800UL)
#define CYREG_PERI_TR_1TO1_GR2_TR_CTL1  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C804UL)
#define CYREG_PERI_TR_1TO1_GR2_TR_CTL2  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C808UL)
#define CYREG_PERI_TR_1TO1_GR2_TR_CTL3  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C80CUL)
#define CYREG_PERI_TR_1TO1_GR2_TR_CTL4  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C810UL)
#define CYREG_PERI_TR_1TO1_GR2_TR_CTL5  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C814UL)
#define CYREG_PERI_TR_1TO1_GR2_TR_CTL6  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C818UL)
#define CYREG_PERI_TR_1TO1_GR2_TR_CTL7  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C81CUL)
#define CYREG_PERI_TR_1TO1_GR2_TR_CTL8  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C820UL)
#define CYREG_PERI_TR_1TO1_GR2_TR_CTL9  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C824UL)
#define CYREG_PERI_TR_1TO1_GR2_TR_CTL10 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C828UL)
#define CYREG_PERI_TR_1TO1_GR2_TR_CTL11 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C82CUL)
#define CYREG_PERI_TR_1TO1_GR2_TR_CTL12 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C830UL)
#define CYREG_PERI_TR_1TO1_GR2_TR_CTL13 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C834UL)
#define CYREG_PERI_TR_1TO1_GR2_TR_CTL14 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C838UL)
#define CYREG_PERI_TR_1TO1_GR2_TR_CTL15 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C83CUL)
#define CYREG_PERI_TR_1TO1_GR2_TR_CTL16 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C840UL)
#define CYREG_PERI_TR_1TO1_GR2_TR_CTL17 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C844UL)
#define CYREG_PERI_TR_1TO1_GR2_TR_CTL18 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C848UL)
#define CYREG_PERI_TR_1TO1_GR2_TR_CTL19 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C84CUL)
#define CYREG_PERI_TR_1TO1_GR2_TR_CTL20 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C850UL)
#define CYREG_PERI_TR_1TO1_GR2_TR_CTL21 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C854UL)

/**
  * \brief Trigger 1-to-1 group (PERI_TR_1TO1_GR3)
  */
#define CYREG_PERI_TR_1TO1_GR3_TR_CTL0  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000CC00UL)
#define CYREG_PERI_TR_1TO1_GR3_TR_CTL1  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000CC04UL)

/**
  * \brief Trigger 1-to-1 group (PERI_TR_1TO1_GR4)
  */
#define CYREG_PERI_TR_1TO1_GR4_TR_CTL0  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D000UL)
#define CYREG_PERI_TR_1TO1_GR4_TR_CTL1  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D004UL)
#define CYREG_PERI_TR_1TO1_GR4_TR_CTL2  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D008UL)
#define CYREG_PERI_TR_1TO1_GR4_TR_CTL3  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D00CUL)
#define CYREG_PERI_TR_1TO1_GR4_TR_CTL4  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D010UL)
#define CYREG_PERI_TR_1TO1_GR4_TR_CTL5  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D014UL)
#define CYREG_PERI_TR_1TO1_GR4_TR_CTL6  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D018UL)
#define CYREG_PERI_TR_1TO1_GR4_TR_CTL7  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D01CUL)
#define CYREG_PERI_TR_1TO1_GR4_TR_CTL8  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D020UL)
#define CYREG_PERI_TR_1TO1_GR4_TR_CTL9  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D024UL)
#define CYREG_PERI_TR_1TO1_GR4_TR_CTL10 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D028UL)
#define CYREG_PERI_TR_1TO1_GR4_TR_CTL11 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D02CUL)

/**
  * \brief Trigger 1-to-1 group (PERI_TR_1TO1_GR5)
  */
#define CYREG_PERI_TR_1TO1_GR5_TR_CTL0  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D400UL)
#define CYREG_PERI_TR_1TO1_GR5_TR_CTL1  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D404UL)
#define CYREG_PERI_TR_1TO1_GR5_TR_CTL2  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D408UL)
#define CYREG_PERI_TR_1TO1_GR5_TR_CTL3  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D40CUL)
#define CYREG_PERI_TR_1TO1_GR5_TR_CTL4  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D410UL)
#define CYREG_PERI_TR_1TO1_GR5_TR_CTL5  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D414UL)

/**
  * \brief Trigger 1-to-1 group (PERI_TR_1TO1_GR6)
  */
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL0  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D800UL)
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL1  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D804UL)
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL2  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D808UL)
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL3  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D80CUL)
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL4  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D810UL)
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL5  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D814UL)
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL6  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D818UL)
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL7  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D81CUL)
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL8  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D820UL)
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL9  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D824UL)
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL10 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D828UL)
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL11 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D82CUL)
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL12 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D830UL)
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL13 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D834UL)
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL14 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D838UL)
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL15 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D83CUL)
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL16 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D840UL)
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL17 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D844UL)
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL18 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D848UL)
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL19 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D84CUL)
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL20 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D850UL)
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL21 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D854UL)
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL22 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D858UL)
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL23 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D85CUL)
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL24 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D860UL)
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL25 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D864UL)
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL26 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D868UL)
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL27 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D86CUL)
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL28 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D870UL)
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL29 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D874UL)
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL30 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D878UL)
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL31 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D87CUL)
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL32 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D880UL)
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL33 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D884UL)
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL34 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D888UL)
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL35 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D88CUL)
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL36 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D890UL)
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL37 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D894UL)
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL38 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D898UL)
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL39 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D89CUL)
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL40 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D8A0UL)
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL41 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D8A4UL)
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL42 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D8A8UL)
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL43 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D8ACUL)
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL44 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D8B0UL)
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL45 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D8B4UL)
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL46 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D8B8UL)
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL47 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D8BCUL)
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL48 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D8C0UL)
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL49 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D8C4UL)
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL50 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D8C8UL)
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL51 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D8CCUL)
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL52 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D8D0UL)
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL53 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D8D4UL)
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL54 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D8D8UL)
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL55 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D8DCUL)
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL56 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D8E0UL)
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL57 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D8E4UL)
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL58 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D8E8UL)
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL59 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D8ECUL)
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL60 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D8F0UL)
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL61 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D8F4UL)
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL62 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D8F8UL)
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL63 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D8FCUL)
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL64 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D900UL)
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL65 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D904UL)
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL66 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D908UL)
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL67 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D90CUL)
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL68 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D910UL)
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL69 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D914UL)
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL70 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D918UL)
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL71 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D91CUL)

/**
  * \brief Trigger 1-to-1 group (PERI_TR_1TO1_GR7)
  */
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL0  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DC00UL)
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL1  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DC04UL)
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL2  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DC08UL)
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL3  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DC0CUL)
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL4  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DC10UL)
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL5  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DC14UL)
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL6  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DC18UL)
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL7  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DC1CUL)
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL8  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DC20UL)
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL9  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DC24UL)
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL10 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DC28UL)
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL11 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DC2CUL)
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL12 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DC30UL)
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL13 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DC34UL)
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL14 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DC38UL)
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL15 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DC3CUL)
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL16 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DC40UL)
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL17 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DC44UL)
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL18 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DC48UL)
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL19 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DC4CUL)
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL20 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DC50UL)
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL21 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DC54UL)
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL22 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DC58UL)
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL23 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DC5CUL)
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL24 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DC60UL)
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL25 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DC64UL)
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL26 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DC68UL)
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL27 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DC6CUL)
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL28 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DC70UL)
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL29 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DC74UL)
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL30 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DC78UL)
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL31 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DC7CUL)
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL32 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DC80UL)
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL33 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DC84UL)
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL34 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DC88UL)
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL35 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DC8CUL)
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL36 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DC90UL)
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL37 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DC94UL)
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL38 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DC98UL)
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL39 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DC9CUL)
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL40 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DCA0UL)
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL41 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DCA4UL)
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL42 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DCA8UL)
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL43 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DCACUL)
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL44 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DCB0UL)
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL45 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DCB4UL)
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL46 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DCB8UL)
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL47 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DCBCUL)
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL48 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DCC0UL)
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL49 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DCC4UL)
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL50 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DCC8UL)
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL51 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DCCCUL)
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL52 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DCD0UL)
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL53 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DCD4UL)
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL54 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DCD8UL)
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL55 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DCDCUL)
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL56 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DCE0UL)
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL57 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DCE4UL)
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL58 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DCE8UL)
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL59 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DCECUL)
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL60 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DCF0UL)
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL61 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DCF4UL)
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL62 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DCF8UL)
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL63 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DCFCUL)
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL64 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DD00UL)
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL65 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DD04UL)
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL66 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DD08UL)
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL67 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DD0CUL)
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL68 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DD10UL)
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL69 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DD14UL)
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL70 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DD18UL)
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL71 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DD1CUL)

/**
  * \brief Trigger 1-to-1 group (PERI_TR_1TO1_GR8)
  */
#define CYREG_PERI_TR_1TO1_GR8_TR_CTL0  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000E000UL)
#define CYREG_PERI_TR_1TO1_GR8_TR_CTL1  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000E004UL)
#define CYREG_PERI_TR_1TO1_GR8_TR_CTL2  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000E008UL)
#define CYREG_PERI_TR_1TO1_GR8_TR_CTL3  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000E00CUL)

/**
  * \brief Trigger 1-to-1 group (PERI_TR_1TO1_GR9)
  */
#define CYREG_PERI_TR_1TO1_GR9_TR_CTL0  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000E400UL)
#define CYREG_PERI_TR_1TO1_GR9_TR_CTL1  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000E404UL)
#define CYREG_PERI_TR_1TO1_GR9_TR_CTL2  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000E408UL)
#define CYREG_PERI_TR_1TO1_GR9_TR_CTL3  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000E40CUL)

/**
  * \brief Trigger 1-to-1 group (PERI_TR_1TO1_GR10)
  */
#define CYREG_PERI_TR_1TO1_GR10_TR_CTL0 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000E800UL)
#define CYREG_PERI_TR_1TO1_GR10_TR_CTL1 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000E804UL)
#define CYREG_PERI_TR_1TO1_GR10_TR_CTL2 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000E808UL)
#define CYREG_PERI_TR_1TO1_GR10_TR_CTL3 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000E80CUL)
#define CYREG_PERI_TR_1TO1_GR10_TR_CTL4 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000E810UL)
#define CYREG_PERI_TR_1TO1_GR10_TR_CTL5 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000E814UL)
#define CYREG_PERI_TR_1TO1_GR10_TR_CTL6 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000E818UL)
#define CYREG_PERI_TR_1TO1_GR10_TR_CTL7 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000E81CUL)
#define CYREG_PERI_TR_1TO1_GR10_TR_CTL8 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000E820UL)
#define CYREG_PERI_TR_1TO1_GR10_TR_CTL9 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000E824UL)
#define CYREG_PERI_TR_1TO1_GR10_TR_CTL10 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000E828UL)
#define CYREG_PERI_TR_1TO1_GR10_TR_CTL11 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000E82CUL)
#define CYREG_PERI_TR_1TO1_GR10_TR_CTL12 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000E830UL)
#define CYREG_PERI_TR_1TO1_GR10_TR_CTL13 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000E834UL)
#define CYREG_PERI_TR_1TO1_GR10_TR_CTL14 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000E838UL)
#define CYREG_PERI_TR_1TO1_GR10_TR_CTL15 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000E83CUL)

/**
  * \brief Peripheral interconnect (PERI0)
  */
#define CYREG_PERI_TIMEOUT_CTL          ((volatile un_PERI_TIMEOUT_CTL_t*) 0x40000200UL)
#define CYREG_PERI_TR_CMD               ((volatile un_PERI_TR_CMD_t*) 0x40000220UL)
#define CYREG_PERI_ECC_CTL              ((volatile un_PERI_ECC_CTL_t*) 0x40002000UL)

#endif /* _CYREG_PERI_H_ */


/* [] END OF FILE */
